1. Field of the Invention
The present invention relates to providing voltages.
2. Description of Related Art
Voltage generating circuits are widely used in electrical and electronic devices. For instance, substrate bias generator circuits, also referred to as back-bias generators, are used in semiconductor devices which require the substrate region to be biased to a predetermined voltage. For example, in dynamic random access memories (DRAM) the substrate region is negatively biased to prevent the DRAM cells from losing the stored information. The back-bias generator includes a voltage multiplier circuit, commonly referred to as charge pump, for providing the negative Back-Bias Voltage (V.sub.BB). The charge pump is usually accompanied by a V.sub.BB detector circuit. The detector circuit regulates the charge pump such that V.sub.BB is maintained as close to a target V.sub.BB value as possible.
The detector circuit constantly senses the V.sub.BB voltage level, and if V.sub.BB becomes more negative than the target V.sub.BB, the detector circuit turns off the charge pump thereby allowing V.sub.BB to drift back to the target V.sub.BB ; and if V.sub.BB becomes less negative than the target V.sub.BB, the detector circuit turns on the charge pump to pump V.sub.BB back to the target V.sub.BB.
FIG. 1 shows a conventional V.sub.BB detector circuit 17. Serially connected resistors R1 and R2 are coupled between the power supply Vcc and V.sub.BB terminal 15. Vcc is provided by a power supply external to the device, and V.sub.BB is generated internally by a charge pump (not shown). Inverter 12 has its input terminal connected to node 11 which is the node between R1 and R2. The output terminal of inverter 12 also provides the output terminal Q10 of the detector circuit 17. Output terminal Q10 is connected to the charge pump.
Vcc, R1, R2, and V.sub.BB form a voltage divider which sets the voltage V.sub.A at node 11 in accordance with the following equation: EQU V.sub.A =[(R2.times.Vcc)+(R1.times.V.sub.BB)]/(R1+R2) (1)
Resistors R1 and R2 are selected so that, for the nominal Vcc value and target V.sub.BB, the voltage V.sub.A equals the trip point of inverter 12. If the charge pump causes V.sub.BB to become more negative than the target value, V.sub.A drops below the trip point of inverter 12 causing Q10 to go high. The high level at Q10 turns off the charge pump, allowing V.sub.BB to increase back to the target value. Alternatively, if V.sub.BB becomes less negative than the target V.sub.BB, V.sub.A rises above the trip point of inverter 12 causing Q10 to go low. The low level of Q10 turns on the charge pump causing V.sub.BB to become more negative. Thus, V.sub.BB is maintained at the target value.
Circuit 17 however, suffers from a number of drawbacks, one of which is that V.sub.BB varies with changes in Vcc. In particular, as shown by equation (1), if Vcc increases, V.sub.BB has to become more negative to keep V.sub.A at the trip point of inverter 12 (this assumes that inverter 12 is designed so that its trip point is insensitive to Vcc). This increases junction leakage as explained in more detail below. The increased junction leakage adversely impacts the operation of the device. For example, in a DRAM the increased junction leakage can cause loss of information stored in the memory cells; and more generally, the high leakage current results in higher static power consumption, e.g., high stand-by current (I.sub.SB).
As both Vcc and .vertline.V.sub.BB.vertline. increase, leakage current increases across the junction between Vcc-biased n+ diffusion regions in the V.sub.BB -biased P-type substrate. This is more clearly illustrated in FIG. 2. FIG. 2 shows a P-type substrate 23 biased to V.sub.BB through the p+ diffusion region 22. The n+ diffusion region 21 represents one of many n+ diffusion regions biased to Vcc. The pn junction formed by the P-substrate 23 and the n+ diffusion 21 is reverse biased since a positive voltage Vcc is applied to the negatively charged n+ diffusion 21 and a negative voltage V.sub.BB is applied to the positively charged P-type substrate 23.
In accordance with the I-V characteristics of a pn junction, as the reverse voltage across the pn junction approaches the junction break down voltage (V.sub.BD), larger leakage current flows through the junction. Therefore, an increase in Vcc and the resulting more negative V.sub.BB, combine to cause a greater reverse voltage across the junction formed by the n+ region 21 and substrate 23.
The undesirable effects of the large leakage currents, such as high I.sub.SB and data loss in DRAM cells, are magnified as technology moves to smaller geometries and memory devices move to higher densities.
Another drawback of circuit 17 (FIG. 1) is that it does not prevent V.sub.BB from becoming positive. If V.sub.BB becomes positive by as little as 0.8V, junctions formed by Vss-biased n+ regions and the V.sub.BB -biased substrate become forward biased. This can lead to latch-up which may destroy the device.
FIG. 3A shows a prior art detector circuit 37 which prevents V.sub.BB from becoming positive. Circuit 37 is identical to circuit 17 of FIG. 1 except that NMOS transistor M30 is connected between node 11 and R2. With the gate of M30 connected to Vss, M30 turns off when its source (lead 33) reaches minus one threshold voltage (-V.sub.TN), V.sub.TN being that of M30. When M30 turns off, V.sub.A rises to Vcc. This causes the charge pump to turn on and pump V.sub.BB to a more negative voltage.
It is desirable to provide an improved V.sub.BB detector.